Implementing a transputer for FPGA in less than 800 lines of code
Publikation: Bidrag til bog/antologi/rapport › Konferencebidrag i proceedings › Forskning › fagfællebedømt
By utilizing Synchronous Message Exchange (SME) for hardware design, we see that going from a hardware schematic to an implementation becomes a much shorter process. This in turn shifts the focus to the architectural details of the implementation. This is shown by constructing an implementation of the Transputer in SME. This implementation has been made in less than 800 lines of code within the timeframe of ∼4 months, where the majority of the time spent has been on the Transputer architecture. The resulting implementation is suboptimal compared to similar projects. However, since no optimizations have been made, reaching a more reasonable resource consumption and clockrate should be attainable within a few months.
Originalsprog | Engelsk |
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Titel | Communicating Process Architectures 2017 and 2018, WoTUG-39 and WoTUG-40 - Proceedings of CPA 2017 (WoTUG-39) and Proceedings of CPA 2018 (WoTUG-40) |
Redaktører | Jan Baekgaard Pedersen, Kevin Chalmers, Jan F. Broenink, Brian Vinter, Kevin Vella, Peter H. Welch, Marc L. Smith, Kenneth Skovhede |
Antal sider | 20 |
Forlag | IMIA and IOS Press |
Publikationsdato | 2019 |
Sider | 559-578 |
ISBN (Elektronisk) | 9781614999485 |
DOI | |
Status | Udgivet - 2019 |
Begivenhed | 39th WoTUG Conference on Communicating Process Architectures, CPA 2017 and 40th WoTUG Conference on Communicating Process Architectures, CPA 2018 - Dresden, Tyskland Varighed: 19 aug. 2018 → 22 aug. 2018 |
Konference
Konference | 39th WoTUG Conference on Communicating Process Architectures, CPA 2017 and 40th WoTUG Conference on Communicating Process Architectures, CPA 2018 |
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Land | Tyskland |
By | Dresden |
Periode | 19/08/2018 → 22/08/2018 |
Navn | Concurrent Systems Engineering Series |
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Vol/bind | 70 |
ISSN | 1383-7575 |
ID: 241091143