Incremental flattening for nested data parallelism

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

Compilation techniques for nested-parallel applications that can adapt to hardware and dataset characteristics are vital for unlocking the power of modern hardware. This paper proposes such a technique, which builds on fattening and is applied in the context of a functional data-parallel language. Our solution uses the degree of utilized parallelism as the driver for generating a multitude of code versions, which together cover all possible mappings of the application's regular nested parallelism to the levels of parallelism supported by the hardware. These code versions are then combined into one program by guarding them with predicates, whose threshold values are automatically tuned to hardware and dataset characteristics. Our unsupervised method-of statically clustering datasets to code versions-is different from autotuning work that typically searches for the combination of code transformations producing a single version, best suited for a specific dataset or on average for all datasets. We demonstrate-by fully integrating our technique in the repertoire of a compiler for the Futhark programming language-significant performance gains on two GPUs for three real-world applications, from the financial domain, and for six Rodinia benchmarks.

Original languageEnglish
Title of host publicationPPoPP 2019 - Proceedings of the 24th Principles and Practice of Parallel Programming
PublisherAssociation for Computing Machinery
Publication date16 Feb 2019
Pages53-67
ISBN (Electronic)9781450362252
DOIs
Publication statusPublished - 16 Feb 2019
Event24th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPoPP 2019 - Washington, United States
Duration: 16 Feb 201920 Feb 2019

Conference

Conference24th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPoPP 2019
LandUnited States
ByWashington
Periode16/02/201920/02/2019
SponsorACM SIGHPC, ACM SIGPLAN

    Research areas

  • Compilers, Functional language, GPGPU, Parallel

ID: 230447731