## Verifying Properties of Bit-vector Multiplication Using Cutting Planes Reasoning

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

#### Standard

**Verifying Properties of Bit-vector Multiplication Using Cutting Planes Reasoning.** / Liew, Vincent; Beame, Paul; Devriendt, Jo; Elffers, Jan; Nordström, Jakob.

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

#### Harvard

*Proceedings of the 20th Conference on Formal Methods in Computer-Aided Design (FMCAD '20).*, 9283622, IEEE, pp. 194-204, 20th International Conference on Formal Methods in Computer-Aided Design - FMCAD 2020;, Virtual, 21/09/2020. https://doi.org/10.34727/2020/isbn.978-3-85448-042-6_27

#### APA

*Proceedings of the 20th Conference on Formal Methods in Computer-Aided Design (FMCAD '20)*(pp. 194-204). [9283622,] IEEE. https://doi.org/10.34727/2020/isbn.978-3-85448-042-6_27

#### Vancouver

#### Author

#### Bibtex

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#### RIS

TY - GEN

T1 - Verifying Properties of Bit-vector Multiplication Using Cutting Planes Reasoning

AU - Liew, Vincent

AU - Beame, Paul

AU - Devriendt, Jo

AU - Elffers, Jan

AU - Nordström, Jakob

PY - 2020/9/1

Y1 - 2020/9/1

N2 - Systems mixing Boolean logic and arithmetic have been a long-standing challenge for verification tools such as SAT-based bit-vector solvers. Though SAT solvers can be highly efficient for Boolean reasoning, they scale poorly once multiplication is involved. Algebraic methods using Gröbner basis reduction have recently been used to efficiently verify multiplier circuits in isolation, but generally do not perform well on problems involving bit-level reasoning. We propose that pseudo-Boolean solvers equipped with cutting planes reasoning have the potential to combine the complementary strengths of the existing SAT and algebraic approaches while avoiding their weaknesses. Theoretically, we show that there are optimal-length cutting planes proofs for a large class of bit-level properties of some well known multiplier circuits. This scaling is significantly better than the smallest proofs known for SAT and, in some instances, for algebraic methods. We also show that cutting planes reasoning can extract bit-level consequences of word-level equations in exponentially fewer steps than methods based on Gröbner bases. Experimentally, we demonstrate that pseudo-Boolean solvers can verify the word-level equivalence of adder-based multiplier architectures, as well as commutativity of bit-vector multiplication, in times comparable to the best algebraic methods. We then go further than previous approaches and also verify these properties at the bit-level. Finally, we find examples of simple nonlinear bit-vector inequalities that are intractable for current bit-vector and SAT solvers but easy for pseudo-Boolean solvers. © 2020 FMCAD Association.

AB - Systems mixing Boolean logic and arithmetic have been a long-standing challenge for verification tools such as SAT-based bit-vector solvers. Though SAT solvers can be highly efficient for Boolean reasoning, they scale poorly once multiplication is involved. Algebraic methods using Gröbner basis reduction have recently been used to efficiently verify multiplier circuits in isolation, but generally do not perform well on problems involving bit-level reasoning. We propose that pseudo-Boolean solvers equipped with cutting planes reasoning have the potential to combine the complementary strengths of the existing SAT and algebraic approaches while avoiding their weaknesses. Theoretically, we show that there are optimal-length cutting planes proofs for a large class of bit-level properties of some well known multiplier circuits. This scaling is significantly better than the smallest proofs known for SAT and, in some instances, for algebraic methods. We also show that cutting planes reasoning can extract bit-level consequences of word-level equations in exponentially fewer steps than methods based on Gröbner bases. Experimentally, we demonstrate that pseudo-Boolean solvers can verify the word-level equivalence of adder-based multiplier architectures, as well as commutativity of bit-vector multiplication, in times comparable to the best algebraic methods. We then go further than previous approaches and also verify these properties at the bit-level. Finally, we find examples of simple nonlinear bit-vector inequalities that are intractable for current bit-vector and SAT solvers but easy for pseudo-Boolean solvers. © 2020 FMCAD Association.

U2 - 10.34727/2020/isbn.978-3-85448-042-6_27

DO - 10.34727/2020/isbn.978-3-85448-042-6_27

M3 - Article in proceedings

SP - 194

EP - 204

BT - Proceedings of the 20th Conference on Formal Methods in Computer-Aided Design (FMCAD '20)

PB - IEEE

T2 - 20th International Conference on Formal Methods in Computer-Aided Design - FMCAD 2020;

Y2 - 21 September 2020 through 24 September 2020

ER -

ID: 251872349