Standard
A reversible processor architecture and its reversible logic design. / Thomsen, Michael Kirkedal; Axelsen, Holger Bock; Glück, Robert.
Reversible Computation: Third International Workshop, RC 2011, Gent, Belgium, July 4-5, 2011. Revised Papers. red. / Alexis De Vos; Robert Wille. Springer, 2012. s. 30-42 (Lecture notes in computer science, Bind 7165).
Publikation: Bidrag til bog/antologi/rapport › Konferencebidrag i proceedings › Forskning › fagfællebedømt
Harvard
Thomsen, MK, Axelsen, HB
& Glück, R 2012,
A reversible processor architecture and its reversible logic design. i A De Vos & R Wille (red),
Reversible Computation: Third International Workshop, RC 2011, Gent, Belgium, July 4-5, 2011. Revised Papers. Springer, Lecture notes in computer science, bind 7165, s. 30-42, 3rd International Workshop on Reversible Computation, Gent, Belgien,
04/07/2011.
https://doi.org/10.1007/978-3-642-29517-1_3
APA
Thomsen, M. K., Axelsen, H. B.
, & Glück, R. (2012).
A reversible processor architecture and its reversible logic design. I A. De Vos, & R. Wille (red.),
Reversible Computation: Third International Workshop, RC 2011, Gent, Belgium, July 4-5, 2011. Revised Papers (s. 30-42). Springer. Lecture notes in computer science Bind 7165
https://doi.org/10.1007/978-3-642-29517-1_3
Vancouver
Thomsen MK, Axelsen HB
, Glück R.
A reversible processor architecture and its reversible logic design. I De Vos A, Wille R, red., Reversible Computation: Third International Workshop, RC 2011, Gent, Belgium, July 4-5, 2011. Revised Papers. Springer. 2012. s. 30-42. (Lecture notes in computer science, Bind 7165).
https://doi.org/10.1007/978-3-642-29517-1_3
Author
Thomsen, Michael Kirkedal ; Axelsen, Holger Bock ; Glück, Robert. / A reversible processor architecture and its reversible logic design. Reversible Computation: Third International Workshop, RC 2011, Gent, Belgium, July 4-5, 2011. Revised Papers. red. / Alexis De Vos ; Robert Wille. Springer, 2012. s. 30-42 (Lecture notes in computer science, Bind 7165).
Bibtex
@inproceedings{9af465e793e44bc393401d3d89dd5cf8,
title = "A reversible processor architecture and its reversible logic design",
abstract = "We describe the design of a purely reversible computing architecture, Bob, and its instruction set, BobISA. The special features of the design include a simple, yet expressive, locally-invertible instruction set, and fully reversible control logic and address calculation. We have designed an architecture with an ISA that is expressive enough to serve as the target for a compiler from a high-level structured reversible programming language.All-in-all, this paper demonstrates that the design of a complete reversible computing architecture is possible and can serve as the core of a programmable reversible computing system.",
author = "Thomsen, {Michael Kirkedal} and Axelsen, {Holger Bock} and Robert Gl{\"u}ck",
year = "2012",
doi = "10.1007/978-3-642-29517-1_3",
language = "English",
isbn = "978-3-642-29516-4",
series = "Lecture notes in computer science",
publisher = "Springer",
pages = "30--42",
editor = "{De Vos}, Alexis and Robert Wille",
booktitle = "Reversible Computation",
address = "Switzerland",
note = "3rd International Workshop on Reversible Computation, RC 2011 ; Conference date: 04-07-2011 Through 05-07-2011",
}
RIS
TY - GEN
T1 - A reversible processor architecture and its reversible logic design
AU - Thomsen, Michael Kirkedal
AU - Axelsen, Holger Bock
AU - Glück, Robert
N1 - Conference code: 3
PY - 2012
Y1 - 2012
N2 - We describe the design of a purely reversible computing architecture, Bob, and its instruction set, BobISA. The special features of the design include a simple, yet expressive, locally-invertible instruction set, and fully reversible control logic and address calculation. We have designed an architecture with an ISA that is expressive enough to serve as the target for a compiler from a high-level structured reversible programming language.All-in-all, this paper demonstrates that the design of a complete reversible computing architecture is possible and can serve as the core of a programmable reversible computing system.
AB - We describe the design of a purely reversible computing architecture, Bob, and its instruction set, BobISA. The special features of the design include a simple, yet expressive, locally-invertible instruction set, and fully reversible control logic and address calculation. We have designed an architecture with an ISA that is expressive enough to serve as the target for a compiler from a high-level structured reversible programming language.All-in-all, this paper demonstrates that the design of a complete reversible computing architecture is possible and can serve as the core of a programmable reversible computing system.
U2 - 10.1007/978-3-642-29517-1_3
DO - 10.1007/978-3-642-29517-1_3
M3 - Article in proceedings
SN - 978-3-642-29516-4
T3 - Lecture notes in computer science
SP - 30
EP - 42
BT - Reversible Computation
A2 - De Vos, Alexis
A2 - Wille, Robert
PB - Springer
T2 - 3rd International Workshop on Reversible Computation
Y2 - 4 July 2011 through 5 July 2011
ER -
