Memory Optimizations in an Array Language

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Standard

Memory Optimizations in an Array Language. / Munksgaard, Philip; Henriksen, Troels; Sadayappan, Ponnuswamy; Oancea, Cosmin.

Proceedings of SC 2022: International Conference for High Performance Computing, Networking, Storage and Analysis. IEEE Computer Society Press, 2022. s. 1-15 31.

Publikation: Bidrag til bog/antologi/rapportKonferencebidrag i proceedingsForskningfagfællebedømt

Harvard

Munksgaard, P, Henriksen, T, Sadayappan, P & Oancea, C 2022, Memory Optimizations in an Array Language. i Proceedings of SC 2022: International Conference for High Performance Computing, Networking, Storage and Analysis., 31, IEEE Computer Society Press, s. 1-15, 2022 International Conference for High Performance Computing, Networking, Storage and Analysis, SC 2022, Dallas, USA, 13/11/2022. https://doi.org/10.1109/SC41404.2022.00036

APA

Munksgaard, P., Henriksen, T., Sadayappan, P., & Oancea, C. (2022). Memory Optimizations in an Array Language. I Proceedings of SC 2022: International Conference for High Performance Computing, Networking, Storage and Analysis (s. 1-15). [31] IEEE Computer Society Press. https://doi.org/10.1109/SC41404.2022.00036

Vancouver

Munksgaard P, Henriksen T, Sadayappan P, Oancea C. Memory Optimizations in an Array Language. I Proceedings of SC 2022: International Conference for High Performance Computing, Networking, Storage and Analysis. IEEE Computer Society Press. 2022. s. 1-15. 31 https://doi.org/10.1109/SC41404.2022.00036

Author

Munksgaard, Philip ; Henriksen, Troels ; Sadayappan, Ponnuswamy ; Oancea, Cosmin. / Memory Optimizations in an Array Language. Proceedings of SC 2022: International Conference for High Performance Computing, Networking, Storage and Analysis. IEEE Computer Society Press, 2022. s. 1-15

Bibtex

@inproceedings{90990534fd3e4e8d9b48a6a4ea4bb533,
title = "Memory Optimizations in an Array Language",
abstract = "We present a technique for introducing and op-timizing the use of memory in a functional array language, aimed at GPU execution, that supports correct-by-construction parallelism. Using linear memory access descriptors as building blocks, we define a notion of memory in the compiler IR that enables cost-free change-of-layout transformations (e.g., slicing, transposition), whose results can even be carried across control flow such as ifs/loops without manifestation in memory. The memory notion allows a graceful transition to an unsafe IR that is automatically optimized (1) to mix reads and writes to the same array inside a parallel construct, and (2) to map semantically different arrays to the same memory block. The result is code similar to what imperative users would write. Our evaluation shows that our optimizations have significant impact (1.1 x -2 x) and result in performance competitive to hand-written code from challenging benchmarks, such as Rodinia's NW, LUD, Hotspot.",
keywords = "functional programming, GPU, op-timizing compiler, parallelism",
author = "Philip Munksgaard and Troels Henriksen and Ponnuswamy Sadayappan and Cosmin Oancea",
note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 2022 International Conference for High Performance Computing, Networking, Storage and Analysis, SC 2022 ; Conference date: 13-11-2022 Through 18-11-2022",
year = "2022",
doi = "10.1109/SC41404.2022.00036",
language = "English",
pages = "1--15",
booktitle = "Proceedings of SC 2022",
publisher = "IEEE Computer Society Press",
address = "United States",

}

RIS

TY - GEN

T1 - Memory Optimizations in an Array Language

AU - Munksgaard, Philip

AU - Henriksen, Troels

AU - Sadayappan, Ponnuswamy

AU - Oancea, Cosmin

N1 - Publisher Copyright: © 2022 IEEE.

PY - 2022

Y1 - 2022

N2 - We present a technique for introducing and op-timizing the use of memory in a functional array language, aimed at GPU execution, that supports correct-by-construction parallelism. Using linear memory access descriptors as building blocks, we define a notion of memory in the compiler IR that enables cost-free change-of-layout transformations (e.g., slicing, transposition), whose results can even be carried across control flow such as ifs/loops without manifestation in memory. The memory notion allows a graceful transition to an unsafe IR that is automatically optimized (1) to mix reads and writes to the same array inside a parallel construct, and (2) to map semantically different arrays to the same memory block. The result is code similar to what imperative users would write. Our evaluation shows that our optimizations have significant impact (1.1 x -2 x) and result in performance competitive to hand-written code from challenging benchmarks, such as Rodinia's NW, LUD, Hotspot.

AB - We present a technique for introducing and op-timizing the use of memory in a functional array language, aimed at GPU execution, that supports correct-by-construction parallelism. Using linear memory access descriptors as building blocks, we define a notion of memory in the compiler IR that enables cost-free change-of-layout transformations (e.g., slicing, transposition), whose results can even be carried across control flow such as ifs/loops without manifestation in memory. The memory notion allows a graceful transition to an unsafe IR that is automatically optimized (1) to mix reads and writes to the same array inside a parallel construct, and (2) to map semantically different arrays to the same memory block. The result is code similar to what imperative users would write. Our evaluation shows that our optimizations have significant impact (1.1 x -2 x) and result in performance competitive to hand-written code from challenging benchmarks, such as Rodinia's NW, LUD, Hotspot.

KW - functional programming

KW - GPU

KW - op-timizing compiler

KW - parallelism

UR - http://www.scopus.com/inward/record.url?scp=85149323721&partnerID=8YFLogxK

U2 - 10.1109/SC41404.2022.00036

DO - 10.1109/SC41404.2022.00036

M3 - Article in proceedings

AN - SCOPUS:85149323721

SP - 1

EP - 15

BT - Proceedings of SC 2022

PB - IEEE Computer Society Press

T2 - 2022 International Conference for High Performance Computing, Networking, Storage and Analysis, SC 2022

Y2 - 13 November 2022 through 18 November 2022

ER -

ID: 341477319