Fast Control for Reversible Processors

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

Standard

Fast Control for Reversible Processors. / Mogensen, Torben Aegidius.

Reversible Computation: 14th International Conference, RC 2022 Urbino, Italy, July 5–6, 2022 Proceedings. ed. / CA Mezzina; K Podlaski. Springer, 2022. p. 51-64 (Lecture Notes in Computer Science, Vol. 13354).

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

Harvard

Mogensen, TA 2022, Fast Control for Reversible Processors. in CA Mezzina & K Podlaski (eds), Reversible Computation: 14th International Conference, RC 2022 Urbino, Italy, July 5–6, 2022 Proceedings. Springer, Lecture Notes in Computer Science, vol. 13354, pp. 51-64, 14th International Conference on Reversible Computation (RC), Urbino, Italy, 05/07/2022. https://doi.org/10.1007/978-3-031-09005-9_4

APA

Mogensen, T. A. (2022). Fast Control for Reversible Processors. In CA. Mezzina, & K. Podlaski (Eds.), Reversible Computation: 14th International Conference, RC 2022 Urbino, Italy, July 5–6, 2022 Proceedings (pp. 51-64). Springer. Lecture Notes in Computer Science Vol. 13354 https://doi.org/10.1007/978-3-031-09005-9_4

Vancouver

Mogensen TA. Fast Control for Reversible Processors. In Mezzina CA, Podlaski K, editors, Reversible Computation: 14th International Conference, RC 2022 Urbino, Italy, July 5–6, 2022 Proceedings. Springer. 2022. p. 51-64. (Lecture Notes in Computer Science, Vol. 13354). https://doi.org/10.1007/978-3-031-09005-9_4

Author

Mogensen, Torben Aegidius. / Fast Control for Reversible Processors. Reversible Computation: 14th International Conference, RC 2022 Urbino, Italy, July 5–6, 2022 Proceedings. editor / CA Mezzina ; K Podlaski. Springer, 2022. pp. 51-64 (Lecture Notes in Computer Science, Vol. 13354).

Bibtex

@inproceedings{4d561ef22e55409b9d4bcc4a6a9c3dba,
title = "Fast Control for Reversible Processors",
abstract = "Reversible processors implemented using reversible gates has a potential for extreme low power dissipation. Very few designs for reversible processors have been made - we are aware only of the Pendulum and Bob processors. The Pendulum processor has a reversible instruction set (PISA), and has been implemented using classical, irreversible logic gates in CMOS. Bob has a gate-level design using reversible gates, but has not been realised in physical hardware.In this paper, we will focus on the control part of reversible processors, assuming very little about the available data-processing instructions and their implementation.The reversible instruction sets PISA and BobISA (the ISA for Bob) use identical control-flow mechanisms that ensure instruction-level reversibility without imposing restrictions on instruction sequences. We review this mechanism and find it relatively costly. So we propose two modifications to the mechanism that allow faster implementation in reversible hardware and which do not significantly complicate code generation. We show a reversible circuit diagram for the complete control step for 16-bit instruction addresses.",
author = "Mogensen, {Torben Aegidius}",
year = "2022",
doi = "10.1007/978-3-031-09005-9_4",
language = "English",
isbn = "978-3-031-09004-2",
series = "Lecture Notes in Computer Science",
publisher = "Springer",
pages = "51--64",
editor = "CA Mezzina and K Podlaski",
booktitle = "Reversible Computation",
address = "Switzerland",
note = "14th International Conference on Reversible Computation (RC) ; Conference date: 05-07-2022 Through 06-07-2022",

}

RIS

TY - GEN

T1 - Fast Control for Reversible Processors

AU - Mogensen, Torben Aegidius

PY - 2022

Y1 - 2022

N2 - Reversible processors implemented using reversible gates has a potential for extreme low power dissipation. Very few designs for reversible processors have been made - we are aware only of the Pendulum and Bob processors. The Pendulum processor has a reversible instruction set (PISA), and has been implemented using classical, irreversible logic gates in CMOS. Bob has a gate-level design using reversible gates, but has not been realised in physical hardware.In this paper, we will focus on the control part of reversible processors, assuming very little about the available data-processing instructions and their implementation.The reversible instruction sets PISA and BobISA (the ISA for Bob) use identical control-flow mechanisms that ensure instruction-level reversibility without imposing restrictions on instruction sequences. We review this mechanism and find it relatively costly. So we propose two modifications to the mechanism that allow faster implementation in reversible hardware and which do not significantly complicate code generation. We show a reversible circuit diagram for the complete control step for 16-bit instruction addresses.

AB - Reversible processors implemented using reversible gates has a potential for extreme low power dissipation. Very few designs for reversible processors have been made - we are aware only of the Pendulum and Bob processors. The Pendulum processor has a reversible instruction set (PISA), and has been implemented using classical, irreversible logic gates in CMOS. Bob has a gate-level design using reversible gates, but has not been realised in physical hardware.In this paper, we will focus on the control part of reversible processors, assuming very little about the available data-processing instructions and their implementation.The reversible instruction sets PISA and BobISA (the ISA for Bob) use identical control-flow mechanisms that ensure instruction-level reversibility without imposing restrictions on instruction sequences. We review this mechanism and find it relatively costly. So we propose two modifications to the mechanism that allow faster implementation in reversible hardware and which do not significantly complicate code generation. We show a reversible circuit diagram for the complete control step for 16-bit instruction addresses.

U2 - 10.1007/978-3-031-09005-9_4

DO - 10.1007/978-3-031-09005-9_4

M3 - Article in proceedings

SN - 978-3-031-09004-2

T3 - Lecture Notes in Computer Science

SP - 51

EP - 64

BT - Reversible Computation

A2 - Mezzina, CA

A2 - Podlaski, K

PB - Springer

T2 - 14th International Conference on Reversible Computation (RC)

Y2 - 5 July 2022 through 6 July 2022

ER -

ID: 326678935