SMEIL: A domain-specific language for synchronous message exchange networks
Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review
Synchronous Message Exchange (SME) is a CSP-derived model for hardware designs implementing globally synchronous message passing. SME implementations currently exist for several general-purpose languages, some of which, are translatable to VHDL for subsequent implementation on hardware. A common SME language could reduce the duplication and feature disparity present in these independent implementations. This paper introduces a domain-specific language for implementing SME designs. It is usable both as a primary implementation language for SME models and as an intermediate target for general-purpose languages. We describe the language, its implementation and its features. Furthermore, we explain the specific requirements for a language within this domain. Finally, we evaluate the language through a number of simple, but realistic, hardware designs by showing how they may be implemented and tested.
Original language | English |
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Title of host publication | Communicating Process Architectures 2017 and 2018, WoTUG-39 and WoTUG-40 - Proceedings of CPA 2017 (WoTUG-39) and Proceedings of CPA 2018 (WoTUG-40) |
Editors | Jan Baekgaard Pedersen, Kevin Chalmers, Jan F. Broenink, Brian Vinter, Kevin Vella, Peter H. Welch, Marc L. Smith, Kenneth Skovhede |
Publisher | IMIA and IOS Press |
Publication date | 2019 |
Pages | 389-414 |
ISBN (Electronic) | 9781614999485 |
DOIs | |
Publication status | Published - 2019 |
Event | 40th WoTUG Conference on Communicating Process Architectures, CPA 2018 - Dresden, Germany Duration: 19 Aug 2018 → 22 Aug 2018 |
Conference
Conference | 40th WoTUG Conference on Communicating Process Architectures, CPA 2018 |
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Land | Germany |
By | Dresden |
Periode | 19/08/2018 → 22/08/2018 |
Series | Concurrent Systems Engineering Series |
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Volume | 70 |
ISSN | 1383-7575 |
- Co-simulation, DSL, FPGA, Hardware design, Intermediate language, SME, VHDL
Research areas
ID: 241090878