Reversible processors implemented using reversible gates has a potential for extreme low power dissipation. Very few designs for reversible processors have been made - we are aware only of the Pendulum and Bob processors. The Pendulum processor has a reversible instruction set (PISA), and has been implemented using classical, irreversible logic gates in CMOS. Bob has a gate-level design using reversible gates, but has not been realised in physical hardware.

In this paper, we will focus on the control part of reversible processors, assuming very little about the available data-processing instructions and their implementation.

The reversible instruction sets PISA and BobISA (the ISA for Bob) use identical control-flow mechanisms that ensure instruction-level reversibility without imposing restrictions on instruction sequences. We review this mechanism and find it relatively costly. So we propose two modifications to the mechanism that allow faster implementation in reversible hardware and which do not significantly complicate code generation. We show a reversible circuit diagram for the complete control step for 16-bit instruction addresses.